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| Grab Life By The Balls Join Date: Jan 2003 Location: Michigan
Posts: 7,835
| Intel readies six-core chip CHIP FIRM Intel is preparing to introduce a six core chip called the "Dunnington", a processor that will pave the way for its Nehalem architecture later this year. According to Eclipse, the “Dunnington” was designed in Bangalore, and will use three dual core 45 nanometre Penryn processors with a shared 16MB L3 cache. Intel readies six-core chip - The INQUIRER Virtualization - Intel Hexes AMD @ ECLIPSE DEVELOPER'S JOURNAL |
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| | #2 |
| Remembering TQ ![]() Join Date: Mar 2001 Location: Sweden
Posts: 13,750
| Re: Intel readies six-core chip This makes me wonder how they accomplished this with the FSB. If there's a buffer type thing on the die to facilitate it, or if they've managed to actually hang even more loads on the same FSB (which would be astounding).
__________________ ![]() Use Firefox - "the one that blocks all the schmutz" Feeling multicore elation? Remember this correlation: Amdahl's Law. |
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| | #3 |
| Moderator ![]() Join Date: May 2003
Posts: 6,688
| Re: Intel readies six-core chip It might have come to being from Intels triple channel DDR memory design thats been talked about already. This might be a Penryn version able to work with a new Nehalem chipset. Just a guess. |
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| | #4 |
| Grab Life By The Balls Join Date: Jan 2003 Location: Michigan
Posts: 7,835
| Re: Intel readies six-core chip Six core's would be sweet but if software really doesnt support quad's yet i dont think it would be a smart move to go to six. |
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| | #5 |
| Moderator ![]() Join Date: May 2003
Posts: 6,688
| Re: Intel readies six-core chip Maybe Intel sees a market for 6 vs. 8 right now. |
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| | #6 |
| Grab Life By The Balls Join Date: Jan 2003 Location: Michigan
Posts: 7,835
| Re: Intel readies six-core chip Or since amd has 3 cores intel adds a 6 core chip. |
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| | #7 |
| Remembering TQ ![]() Join Date: Mar 2001 Location: Sweden
Posts: 13,750
| Re: Intel readies six-core chip This is for the current FSB-based sockets (being Penryn cores) which means if they want triple-channel, it has to go on the chipset. And as far as I know, the Nehalem chipsets (that anyone cares about) won't come with memory controllers, or FSBs for that matter. Methinks it's stretching the current platform a bit more, providing high-density drop-in replacements for loads that love CPU but don't need a lot of memory bandwidth (since 6 cores over a single FSB will have a per-CPU memory bandwidth of exactly crap GB/s).
__________________ ![]() Use Firefox - "the one that blocks all the schmutz" Feeling multicore elation? Remember this correlation: Amdahl's Law. |
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