SSE5 became AVX + XOP

[Kedas]

A look at amd's avx and xop - The Inquirer

A FEW DAYS AGO, AMD announced that it would support Intel's AVX instruction set rather than continuing on with SSE5. This stops any fragmentation and lets the best implementation win.

SSE5 is a superset of AVX. AMD put the bits not covered in another ISA called XOP, so with one exception, SSE5 became AVX + XOP. When Sandy Bridge and Bulldozer come out, we will get a chance to see how each one is done, and what the various strengths and weaknesses are.

So we don't have to worry about that anymore.
The question now will be who did the best job in implementing the instruction sets.
Not sure if intel has a time advantage over AMD since AMD started SSE5 sooner than intel started AVX I assume.

[CrowdAds]

[Kedas]

more info here: AMD Developer Blogs
Striking a Balance

It seems only CVT16 (half-precision floating point converts) and FMA3 instead of FMA4 would delay AMD's planning for the 2011 launch of Bulldozer, so they decide not to include it in the first bulldozer versions.

So unless intel is playing dirty and changes some important things next year, bulldozer will have the same instruction sets as intel with a minor FMA difference and on top of it AMD will have one more set XOP (SSE5 that was not present in AVX)