Saw this story...maybe you are interested.

[hansje]

I can't be wrong....is this an interesting story ??

Just want to share it....on my favourite-Forum

http://www.madshrimps.be/?action=getarticle&articID=92

hansje

[Ralf Hutter]

Suprised no one's commented yet. I tend to agree with him. There certainly is some weirdness with the way the 865/875 chipsets work with certain RAM. This would explain some of it.

[k0NG0]

I think he's a bit of a drama queen.

Claiming the MCH is flawed because he can't do a 30-50% overclock is just silly. Intel sells the product validated at the stock speed, and it will run that. Above that speed, there are no guarantees. That PAT would indeed be a contributor to shaky reliability when the clock speed increases isn't a bad bet. If you have a technology that's pushed the envelope even further at stock speed than before, you can be sure it'll break sooner too.

He also says something about Granite Bay being based on RDRAM. That's not true. It's a 100% DDR solution, the i850E was the last of the RDRAM chipsets - the code name was Tehama-E. The designs are very much different from eachother and the little picnic Intel had with the i820 and MTH, you can be sure they didn't just bolt on DDR support on the i850E.

He also goes on and on about his very good and logical way of testing. He tested 3 motherboards for heaven's sake. That's 3 chipset out of thousands and thousands. Claiming to have evidence for a flawed product based on that isn't wise. And although he mentions that if you change one variable in a test you can invalidate the test completely, he makes several parallels to other review sites commentary. Isn't that a contradiction?

Concerning Intel binning chips, I would say that they would most likely do that if an MCH fails PAT at stock speed or in that region. Intel have no reason to test a product with a large overclock, since they don't sell overclocking products. It is also possible that PAT, if utilized, needs extra grounds to make things tick the way they're supposed to, hence more ground pins needed. It's also common practise to add ground pins for a more stable operation (the jump from 432 to 478 pins were largely attributed to extra ground and voltage pins for the Pentium 4 IIRC). This would be logical in the case of the Canterwood, since the constant pressure on Intel to guarantee a solid product for their big corporate customers will mean that they'll do that, and add extra cost while doing so. The Springdale is validated to run at stock speed with the pins they have on it. I'm sure they cut as many as possible to make the chipset cheaper for them to make, meaning more profit per chip - and the cheaper price they sell it for will mean they sell more of it too.
I don't think they have the ability to base the entire Springdale manufacturing on binning. They're probably selling a set quantity as Springdales, whereas the production lines are identical. That they are the derivatives of the same basic design is a very much likely thing.

On the other hand, RAM not working at stock speed would be a problem for Intel. But as he says.

"In fact most memories, albeit DDR500, or DDR400 work perfectly fine at default settings on 875/865 platforms, which is 200FSB at 1:1 ratio (Auto in most cases) and at SPD timings. Therefore, the gist of Intel's chipsets will never be pushed beyond default settings, and the anomaly will go unnoticed."

How can it be an anomaly and a flawed product when it does what it's supposed to when it's supposed to do it. Sure, he can't overclock the snot out of it without having to pull the plug, that's his problem not Intel's. Accusing them of putting out a bad project is juvenile and silly. At least if you ask me.

Edit: He goes on about the numerous BIOS revisions from Abit claiming this could be because of a bad chipset. It could also mean Abit has crap BIOS programmers, but he doesn't mention that.

-kONGO

[dream caster]

see the same problem in Corsair's forum:
from a sligthly different point of view and more condensed; i would sum it up this way:

• PAT introduces a hidden incompatibility that prevents correct AUTO set up of memory timings for newer memory ic's that use >5ns cycle time; springdale, by not having PAT activated in hardware, does not suffer this; overclocking the 875 suffers because of this.

As Liquid3D, the author of the article linked in the first post, says in Corsair's forum:

In PAT's "imposing" latency demands, I beleive there exists a conflict. Sudhian as identified this as the chipset's inability to run tRAS-2, which the newer DDR500 has as a value in it's SPD (Serial Presence Detect) settings.

EDIT:i found the sudhian article
High-End, High-Performance: Eight Canterwood Boards Reviewed.
go to the second page to RAM Support and Canterwood:

[bigtoe]

Guys i have been saying this for WEEKS, NO 2 chipsets on any 875 or 865 board act the same. Its causing ALL sorts of problems for OCZ and Corsair and probably everyone else who supplies fast ddr memory.

You either get a good board, or a bad one, but 90% of the time the memory is blamed!

I think its time Intel told us what the problem is or let one of the mobo manufacturers tell us.

[bigtoe]

Im going to stick this one for a short while as i think is deserves a read.

[Ralf Hutter]

Originally posted by bigtoe
Guys i have been saying this for WEEKS, NO 2 chipsets on any 875 or 865 board act the same.

Hey, I've been saying it too but I'm not as knowledgable or as famous as you so even less people listen to me!

[k0NG0]

Do these said RAM problems pertain at stock speeds too? If so, Intel do have some things to check out.

I think Intel won't spend much effort if all these problems are happening in an overclocked environment, that's for sure. Sad but true - and probably a wise business decision too (cost vs. revenue, that is).

-kONGO

[Ralf Hutter]

Originally posted by kONGO
Do these said RAM problems pertain at stock speeds too? If so, Intel do have some things to check out.
-kONGO

Yes, absolutely. Check out the giant 875PBZ thread and search the forums for other 875PBZ posts.

I have personally experienced memory timing variations/oddities using the same sticks of RAM on three different 875PBZ boards, all at DDR400 speed, no OCing at all.

[k0NG0]

Originally posted by Ralf Hutter
Yes, absolutely. Check out the giant 875PBZ thread and search the forums for other 875PBZ posts.

I have personally experienced memory timing variations/oddities using the same sticks of RAM on three different 875PBZ boards, all at DDR400 speed, no OCing at all.

Will do. I'm also checking the JEDEC DDR spec to see if there's something there that could be interesting. So far I'm trying to come to terms with the different memory timing values. tRCD is mentioned as RAS-to-CAS latency in the hardware site texts, but the spec talks about ACTIVE to READ or WRITE delay (I figure they are the same thing, hehe), and has a measurement in nanoseconds (tRCD > 15ns for DDR400). Trying to figure out what that means when compared to the number 2 that's been mentioned (if it's 2 clock cycles, that would be 10ns and thus out of spec, so I doubt that's it).

Off to the giant thread. Oh dear.

Edit: changed the value for tRCD from the JEDEC spec - it's 15ns minimum according to the datasheet. To me that would mean a 3 cycle minimum at 200MHz (5ns cycle time). Reading some more...

-kONGO

[k0NG0]

Can't wrap my brain around the JEDEC datasheet just yet. There's a tCK value (supposedly clock cycle time) that I don't quite understand. It's 5ns for CAS=2.3 and CAS=3, but for CAS=2 it's 7.5ns. I figured DDR400 would be 5ns clock regardless of CAS setting - maybe they are different things (maybe with a CAS setting of 2, the datarate is still 400MHz per pin, and all is well - I haven't checked that, too tired).

Anyway, the tRCD is defined for DDR400 as 15ns minimum. With a 5ns clock, that means 3 cycles, and a tRCD of 3 in the BIOS. But, if - for CAS=2 - the clock is 7.5ns, that would mean a tRCD of 2 is OK.

Also, the tRC should then be OK at 8 with CAS=2.5 and CAS=3, but with CAS=2 you should be able to set tRC=6.

With the knowledge I've gained this far (and I'm not saying I'm right), that should mean that 2-2-2-6 is indeed a DDR400 certified speed to run at, although it's the fastest the standard would allow. Intel would then have a board that doesn't run JEDEC spec'ed RAM and should take care of it.

Bah, enough of this today. If anyone wants the DDR spec I've put it up on my server. Please download it and read it from your HDD, don't use the Acrobat Reader web browser plug-in.

JEDEC DDR Specification linky

The table with interesting data is on page 50 of the specification (or Acrobat page 56 - there's a lot of legal fluff before the document actually starts with page 1).

-kONGO

[ZenmasteR]

sort of confirms my original experience,

I couldnt be bothered so I went back to 850E based P4T533C..


I will wait it out till something more revolutionary is released.
(return of rambus )

[dream caster]

May be not the same but could be related:

Originally posted by MeowChow in OCAU

I have some DDR modules (sammy E-TCCC) that are capable of 235-260 FSB @ 2.8V, but when I turn on the 5:4 divider, with an IC7 mb and 2.4C cpu that I know go 290+ (with different RAM), the memory suddenly maxes out at 216-220. What gives? I've memtested stable at 1:1 235 mem, but at 5:4 even 218 mem gives immediate memory (single-bit) errors.

I'm stumped. Any ideas?

Posted a link to this thread there.

[hansje]

Originally posted by bigtoe
Im going to stick this one for a short while as i think is deserves a read.

This is my first STICKY in my whole life

Once I have done something useful...thanks Bigtoe

hansje

[Jim Bimby]

Hi all !

Great sticky and very interesting article.

Is my summary of this issue correct as follows:-

=> if you stick with Cas3 settings, you can run your memory at (i) any ratio you want and (ii) therefore max' out your cpu and ram as best you can ie: the issues mentioned in this article *only* arise when people are running their DDR in these boards at Cas 2 or Cas 2.5

Is this a fair / correct summary ?

Jim