A lame excuse from VIA?

[Torstein]

In the latest issue of the german publication c’t is an article “Chip-Designer auf Bug-Jagd” (which translates to something like “chip designer hunting bugs”). The ingress further states that a representative of VIA blames their recent problem with the Southbridge chip 686B on “holes” in the PCI-specification i.e. omissions or insufficiences in the Intel originated spec. By any standards a rather lame excuse for an attempt to exceed the bandwidth of the PCI-bus by fiddling with the concept of bus-mastering.
Since the ASUS A7V133 board is one affected by the 686B “bug” and that so many AMD users (read AMD fans) deny its existence, the article in the german semi professional magazine may be an interesting read to the members of the ASUS Board Forum , that is if you read german.
For those who do not, let me try to translate an excerpt from the last paragraph :
“ -- for those (firms) that want to gain acceptance for supplying stable and reliable hardware it is a prerequisite that they must document the often unavoidable faults that occur – and not to leave the user to live with rumours ----“
Pretty strong words (and a fairly long sentence) if you ask me.

The reason why I got caught by the underlying message above, is that I tried (in vain) to build a system based on VIA’s chipset MPV3 a year ago. For the hours and days I spent on trying to get VIA’s various 4in1 drivers to play along with Matrox drivers and Microsofts K6-updates I only learned one thing: Rely on factual information from reliable sources (like this forum )


System:
CUSL2 PIII 700@1003MHz 1,85V FOP32 BIOS1006.beta
2xVitalec 128mb/133MHz at 222 5/7