Official Conroe information thread

[shaihulud]

Since some people are looking for information and I am an advocate of core logic knowledge (this is not a pun), I think you all will find this article impressive. From the many sources of what I have read this chip is an internal masterpiece and very impressive. What catches my eye the most is the 128bit SSE units.

http://www.realworldtech.com/page.cf...WT030906143144

[h20-ski]

Well someone on Xtremesystems.org has gotten a hold of a Conroe. The link is here. I will be watching for sure.

[Sandog]

Originally Posted by Intel_User

Very funny. I always had high hopes for Core Duo(aka Yonah) and reviewers always benchmarked it wrong, making it look bad than its supposed to be .

Intel 945 chipset supports 1066MHz FSB, yet it doesn't have any CPUs supported that runs at 1066MHz FSB: http://www.intel.com/products/chipsets/945g/index.htm

I wonder if it has to do with Conroe. I'll probably get G965 since the integrated graphics core so far looks so sweet.

I read that the G965 graphics chip (ATI maybe?) is suppose to be Vista ready. It will be very good onboard graphics as far as business standards require.

[Sandog]

Originally Posted by shaihulud

Since some people are looking for information and I am an advocate of core logic knowledge (this is not a pun), I think you all will find this article impressive. From the many sources of what I have read this chip is an internal masterpiece and very impressive. What catches my eye the most is the 128bit SSE units.

http://www.realworldtech.com/page.cf...WT030906143144

Official Conroe information thread

[Sandog]

Originally Posted by h20-ski

Well someone on Xtremesystems.org has gotten a hold of a Conroe. The link is here. I will be watching for sure.

I believe he is the one who posted the first D975XBX pics I saw on the web that I linked to so you can count on him. I'm pretty sure he's a professional photographer.

[shaihulud]

That is what I get for skiming over rather than reading. You always have a post or a few that do not register.

[Sandog]

Actually I haven't gone through the whole article and you said something I hadn't read. It's nice to read up on and admire the design implementation/technology of the new Conroe but the bottom line will be how it actually performs in a computer case. I have no doubt though that the performance will be sweet.

PS. I will try to have my posts register certified from now on

[h20-ski]

Ya the guy in that forum was even able to do a bulk order for T2600 ES's for members of the forum. I wish that I could be in his shoes.:eek:

[DeusExMachina]

Originally Posted by h20-ski

Ya the guy in that forum was even able to do a bulk order for T2600 ES's for members of the forum. I wish that I could be in his shoes.:eek:

Hmmmmm, that maybe a sweet idea. A benefit for membership????

DXM

[shaihulud]

When I read into the execution pipelines, I was surprised. Even the cache architecture, which Intel always has had as very robust, is not in contention with the second core. The decoder, branch, retirement...........there is not one part of it so far that I find it to be a bad idea or consequential. This is built to be a really nice chip.

“.......decodes 4+1 x86 instructions, issues 7 uops, reorders and renames 4 uops, dispatches 6 uops to execution units and retires up to 4 uops each cycle.” Wow!

[Sandog]

Originally Posted by shaihulud

“.......decodes 4+1 x86 instructions, issues 7 uops, reorders and renames 4 uops, dispatches 6 uops to execution units and retires up to 4 uops each cycle.” Wow!

...x2.

[Intel_User]

Since some people are looking for information and I am an advocate of core logic knowledge (this is not a pun), I think you all will find this article impressive. From the many sources of what I have read this chip is an internal masterpiece and very impressive. What catches my eye the most is the 128bit SSE units.

http://www.realworldtech.com/page.cf...WT030906143144

The SSE units are not symmetric but neverthless impressive. It means the LEAST amount of throughput on SSE on Core Microarchitecture would be SAME as BEST throughput on previous gen CPUs like Pentium 4/Yonah.

At best it can do: "In comparison, the Core CPU can perform 4 DP FLOPS/cycle and then some: a 128 bit multiply, a 128 bit add, a 128 bit load, a 128 bit store and then perhaps an ALU or fused compare and jump instruction in the last dispatch port."

I have seen Intel's Presentation on PDF. It basically says same thing as link.

I was surprised. Even the cache architecture, which Intel always has had as very robust, is not in contention with the second core.

Not sure what you mean by its not in contention. If its seperate cache then its not in contention but Core has shared caches. But it has a very good shared cache implementation so its better than non shared. Its supposed to have dynamic allocation of bandwidth and cache space depending on the load of two cores.

Shared caches were already good in Yonah. I am sure its improved in Core but its negligible compared to other enhancements.

[Intel_User]

http://www.computerbase.de/news/hard...ore_duo_merom/

Merom 2.0GHz
Yonah 2.167GHz

3Dmark06
M: 941
Y: 808
3Dmark01SE
M: 17163
Y: 15845
PCMark04
M: 6940
Y: 6544
3Dmark03
M: 5140
Y: 5130
PCMark05
M: 4309
Y: 4213
3Dmark05
M: 2442
Y: 2279

Both systems used 1GB DDR2 and Mobility Radeon X1400.

According to what I have seen over the net, Merom is 15-20% faster PER CLOCK compared to Yonah, with same chipset, same FSB. Now doubled cache sizes only make 3-4% difference in 3DMark tests. The rest are architectural advancements. Core is simply amazing.

[shaihulud]

You will usually find that units used are particular to a function therefore will not always be symmetrical. The diagram does not map this out, but the literature does clarify some. Yes, 128bit units, and now compare them to the previous 64bit architectures and the instruction flow to them. This is nice no matter how you look at it. As you have noted and so have I have, it will perform quite well.

The notation you used is better expanded:
"The Core microarchitecture also substantially improves on the floating point and SSE capabilities of its predecessors. Although Core’s 3 SSE units are not fully symmetric, the differences are relatively minor (shifting and multiplication resources). The SSE units are fully pipelined and each one can execute the appropriate 128 bit SSE operation in a single cycle. In comparison, the P4’s SSE resources are somewhat scanty; the two 64 bit SSE units use two cycles to execute 128 bit operations, and therefore are only partially pipelined. Similarly, Yonah only has 64 bit data paths. In comparison, the Core CPU can perform 4 DP FLOPS/cycle and then some: a 128 bit multiply, a 128 bit add, a 128 bit load, a 128 bit store and then perhaps an ALU or fused compare and jump instruction in the last dispatch port."

There is always contention with cache and multiprocessors. How the contention is alleviated depends on the architecture and coherency model used. I am not as pleased with the previous methods used. This design is more for a dual core SMP implementation. Where as, even with HyperTransport, the method AMD uses seems archaic to me. Core's ability to work with its recourses within itself and outside itself is more robust and modern without a doubt.

"The shared L2 cache for the Core MPU is a non-inclusive, non-exclusive design. Latency numbers were not disclosed, but it is very likely that the L1D cache latency is 2-3 cycles, most likely 2. As previously mentioned, Core can transfer directly between the L1D caches in some variants. However, it is currently unknown how often this transfer can occur, how much data is transferred (probably a cache line) and whether such a transaction would replace an L2 cache access. The Core memory subsystem also implements new prefetchers designs to work effectively with shared caches. Each L1D cache has several prefetchers, and the L2 prefetchers dynamically allocate bandwidth between the two CPUs based on the data access patterns and intensity using a modified round-robin algorithm. The front-side bus is similarly arbitrated for fairness."

[Intel_User]

Ah, ok, still not 100% clear but better now .

Intel's Israel design center+mobile team rocks!! I heard new design will be out in two years!!! Better architecture than Conroe+maybe IMC=wow that's gonna be unbelievable.