AMD's Optimization Guide for 10h

[shaihulud]

I have been reading on the new processor from AMD. One of my biggest questions have been answered, it seems. I was curious if the SSE4 instruction set was to be supported and apparently it is. In the optimization guide it is referenced as SSE4a. I am wondering if this is Penryn's set of SSE4 instructions, and SSE4b will be the latter to come as we all know from Intel's new architecture?

Other questions that I already had answers to, such as the L3 cache being a victim cache, was true also. However, this was easy due to the fact of Athlon XP/64 cache architecture. This actually disappoints me a bit, and even with some of the improvements I do not think AMD will ever meet the ability Intel's cache architecture. But there are some new direct load to L1 features for 10h that makes me all so curious.

Anyways here is the link to the processor's optimization guide: http://www.amd.com/us-en/assets/cont...docs/40546.pdf

[k0NG0]

Don't they use the L2 as a victim cache for the L1 (or at least L1D) in K8, too?

Intel still uses an inclusive cache hierarchy, from what I know, which has different characteristics when it comes to misses. I believe AMD has traditionally favored an exclusive hierarchy, although my own memory certainly could use refreshing, being DRAM and all.

[shaihulud]

For the K8 and XP, the victim buffer is before L2. This way if an evict is sent out of L1 it is not fully lost if a miss occurs in L1. Without the victim buffer the total cycles will still be of L1+L2. It checks the victim buffer first if present then it will move, in a fast manner, back to L1. If not in victim then it will most likely be present in L2, and then sent to L1. If not in L2 then it will be a fetch, and many cycles would have been wasted.

So now, with the new processor, there is a victim buffer between the individual cores L1 and L2, and then an L3 victim buffer that all the cores victim and copy backs from L2 go to.