ABXZone Computer  Forums

Thread Tools Display Modes
Old 04-06-2005, 03:40 PM   #1
Registered User
Join Date: Sep 2003
Posts: 13,880
NF4 "memory settings explained" thread

On many newer nForce boards, there are a lot of memory settings in the BIOS. So what do they do? Most motherboard manuals offer no explanations. But fortunately there is good information available on the web. Feel free to contribute any knowledge you might have to this thread.

How RAM works

A short intro to SDRAM
LostCircuits has a very good introductory guide to memory. Link

What do those memory settings do?
Adrian Wong also has a good BIOS optimization guide that you should all bookmark. His latest guide can be found at Rojakpot.com

Drive strength
Sometimes called driving strength. No, it's not about cars. This feature allows you to control the memory data bus' signal strength. Increasing the drive strength of the memory bus can increase stability during overclocking.

DQS skew
Again, I turn to LostCircuits for an explanation. Link

"It is true that lower voltage swings enable higher frequencies but after a certain point, the ramping of the voltages will show a significant skew. The skew can be reduced by increased drive strength, however, with the drawback of a voltage overshoot / undershoot at the rising and falling edges, respectively. One additional problem with high frequency signalling is the phenomenon of trace delays. The solution in DDR was to add clock forwarding in form of a simple data strobe. DDR II takes things further by introducing a bidirectional, differential I/O buffer strobe consisting of DQS and /DQS as pull-up and pull-down signals. Differential means that the two signals are measured against each other instead of using a simple strobe signal and a reference point. In theory the pull-up and pull-down signals should be mirror-symmetric to each other but reality shows otherwise. That means that there will be skew-induced delays to reaching the output high and low voltages (VOH and VOL) and the cross points between DQS and /DQS used for clock forwarding will not necessarily coincide with the DQ crossing the reference voltage (Vref) or even be consistent from one clock to the next. The mismatch between clock and data reference points is referred to as the DQ-DQS skew."

More to follow.

Last edited by Sierra_abx; 04-07-2005 at 04:10 PM..
(Offline)   Reply With Quote

Advertisement [Remove Advertisement]
Old 04-06-2005, 04:54 PM   #2
Registered User
Join Date: Sep 2003
Posts: 13,880
tRAS explained

From Adrian Wong's BIOS optimization guide:

"Like DRAM Act to PreChrg CMD, this BIOS feature controls the memory bank's minimum row active time (tRAS). This constitutes the time when a row is activated until the time the same row can be deactivated.

If the tRAS period is too long, it can reduce performance by unnecessarily delaying the deactivation of active rows. Reducing the tRAS period allows the active row to be deactivated earlier.

However, if the tRAS period is too short, there may not be enough time to complete a burst transfer. This reduces performance and data may be lost or corrupted.

For optimal performance, use the lowest value you can. Usually, this should be CAS latency + tRCD + 2 clock cycles. For example, if you set the CAS latency to 2 clock cycles and the tRCD to 3 clock cycles, the optimum tRAS value would be 7 clock cycles.

But if you start getting memory errors or system crashes, increase the tRAS value one clock cycle at a time until your system becomes stable."

On NF2 & NF3 boards, 11 was often the recommended tRAS setting. But tests done by Anandtech on the DFI NF4 SLI-DR found that 6 was the best bandwidth setting for many memory modules. Link

Last edited by Sierra_abx; 04-06-2005 at 05:07 PM..
(Offline)   Reply With Quote
Old 04-07-2005, 07:32 AM   #3
Registered User
eva2000's Avatar
Join Date: Jul 2001
Location: Brisbane, Australia
Posts: 1,674
Interesting stuff although i don't understand it all LOL
(Offline)   Reply With Quote
Old 04-07-2005, 08:27 AM   #4
Revolutionary Mule
Eldonko's Avatar
Join Date: Nov 2004
Location: Calgary, AB
Posts: 2,987
GJ Sierra. Do you have any info in tref? I'm still trying to figure that one out.

To view links or images in signatures your post count must be 10 or greater. You currently have 0 posts.

PM me for Mushkin questions or support.
(Offline)   Reply With Quote
Old 04-07-2005, 01:12 PM   #5
Registered User
Join Date: Sep 2003
Posts: 13,880
tREF explained

The information below is taken from an old RAM guide. In a nutshell a memory module is made up of electrical cells. The refresh process recharges these cells, which are arranged on the chips in rows. The refresh cycle refers to the number of rows that must be refreshed.

"Periodically the charge stored in each bit must be refreshed or the charge will decay and the value of the bit of data will be lost. DRAM (Dynamic Random Access Memory) is really just a bunch of capacitors that can store energy in an array of bits. The array of bits can be accessed randomly. However, the capacitors can only store this energy for a short time before it discharges it. Therefore DRAM must be refreshed (re-energizing of the capacitors) every 15.6Ás (a microsecond equals 10-6 seconds) per row. Each time the capacitors are refreshed the memory is re-written. For this reason DRAM is also called volatile memory.

Using the RAS-ONLY refresh (ROR) method, the refresh is done is a systematic manner, each column is refreshed row by row in sequence. In a typical EDO module each row takes 15.6Ás to refresh. Therefore in a 2K module the refresh time per column would be 15.6Ás x 2048 rows = 32ms (1 millisecond equals 10-6 seconds). This value is called the tREF. It refers to the refresh interval of the entire array."
(Offline)   Reply With Quote
Old 04-07-2005, 03:57 PM   #6
Registered User
Join Date: Sep 2003
Posts: 13,880
Idle cycle limit

Idle cycle limit - Some BIOS interfaces offer the selection of specifying the SDRAM idle cycle limit. The idle cycle limit is the number of clock cycles that a page is allowed to stay open even if there is no access. The relevance of this setting is that in cases where intermittent accesses to the cache are made or else, the CPU does not issue any read requests, the controller is still able to go back to the same page even after some idle cycles. Whether setting the idle cycle timer shorter or longer results in more performance, depends on the application.
(Offline)   Reply With Quote

Thread Tools
Display Modes

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off

Forum Jump

Powered by vBulletin® Copyright ©2000 - 2018, Jelsoft Enterprises Ltd.
vBulletin Skin developed by: vBStyles.com

© 2006 - 2016 ABXZone Forums | About ABX Zone Forums | Advertisers | Investors | Legal | A member of the Crowdgather Forum Community